The Cell Broadband Engine (Cell/B.E.) is a 64-bit reduced instruction set computer (RISC) multi-core processor and microarchitecture developed by Sony, Toshiba, and IBM—an alliance known as "STI". It combines several elements: a general-purpose PowerPC core, named the Power Processing Element (PPE); and multiple specialized coprocessors, known as Synergistic Processing Elements (SPEs), which accelerate tasks such as multimedia and vector processing.
The architecture was developed over four years, beginning in March 2001, with Sony reporting a development budget of approximately US$400 million. Its first major commercial application was in Sony's PlayStation 3 (PS3) home video game console, released in 2006. In 2008, a modified version of the Cell processor powered IBM's Roadrunner, the first supercomputer to achieve sustained one-petaFLOPS performance. Other applications include high-performance computing systems from Mercury Computer Systems and specialized arcade system boards.
Cell emphasizes memory coherence, power efficiency, and peak computational throughput, but its design presented significant challenges for software development. IBM offered a Linux-based software development kit (SDK) to facilitate programming on the platform.
History
In the mid-2000s, Sony, Toshiba, and IBM formed the STI alliance to develop a new microprocessor. The STI Design Center opened in March 2001 in Austin, Texas. Over the next four years, more than 400 engineers collaborated on the project, with IBM contributing work from eleven of its design centers.
Initial patents described a configuration with four Power Processing Elements (PPEs), each paired with eight Synergistic Processing Elements (SPEs), for a theoretical peak performance of 1 teraFLOPS. However, only a scaled-down design—one PPE with eight SPEs—was ultimately manufactured.
Fabrication of the initial Cell chip began on a 90 nm silicon on insulator (SOI) process (i.e., lithographic node). In March 2007, IBM transitioned production to a 65 nm process, followed by a 45 nm process announced in February 2008. The video game publisher Bandai Namco Entertainment used the Cell processor in its Namco System 357 and 369 arcade boards.
In May 2008, IBM introduced the PowerXCell 8i, a double-precision variant of the Cell processor, used in systems such as IBM's Roadrunner supercomputer, the first to achieve one petaFLOPS and the fastest until late 2009.
IBM ceased development of higher-core-count Cell variants (such as a 32-APU version) in late 2009, but it continues to support existing Cell-based products.
Commercialization
On May 17, 2005, Sony confirmed the Cell configuration used in the PlayStation 3: one PPE and seven SPEs. To improve manufacturing yield, the processor is initially fabricated with eight SPEs. After production, each chip is tested, and if a defect is found in one SPE, it is disabled using laser trimming. This approach minimizes waste by utilizing processors that would otherwise be discarded. Even in chips without defects, one SPE is intentionally disabled to ensure consistency across units. Of the seven operational SPEs, six are available for developers to use in games and applications, while the seventh is reserved for the console's operating system. The chip operates at a clock speed of 3.2 GHz. Sony also used the Cell in its Zego high-performance media computing server.
The PPE supports simultaneous multithreading (SMT) and can execute two threads; each active SPE supports one thread. In the PlayStation 3 configuration, the Cell processor supports up to nine threads.
On June 28, 2005, IBM and Mercury Computer Systems announced a partnership to use Cell processors in embedded systems for medical imaging, aerospace, and seismic processing, among other applications. Mercury uses the full Cell processor with eight active SPEs. Mercury later released blade servers and PCI Express accelerator cards based on this architecture.
In 2006, IBM introduced the QS20 blade server, which offers up to 410 gigaFLOPS per module in single-precision performance. The QS22 blade server, based on the PowerXCell 8i processor, was used in IBM's Roadrunner supercomputer. On April 8, 2008, Fixstars Corporation released a PCI Express accelerator board based on the PowerXCell 8i.
According to a former IBM executive, IBM planned for Apple to move its Mac line to the Cell before the transition to Intel processors.
Overview
The Cell Broadband Engine, or "Cell" as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the Athlon 64 and the Core 2 families) and more specialized high-performance processors (such as the NVIDIA and ATI graphics processing units [GPUs]). The longer name indicates its intended use, namely, as a component in current and future online distribution systems; as such, it may be used in high-definition displays and recording equipment, as well as HDTV systems. In addition, the processor may be suited to digital imaging systems (e.g., medical and scientific) and physical simulation (e.g., scientific and structural engineering modeling). As used in the PlayStation 3, the processor has 250 million transistors.
In a simple analysis, the Cell processor can be divided into four components:
- external input and output structures
- the main processor, called the Power Processing Element (PPE)—a two-way simultaneous-multithreaded PowerPC 2.02 core
- eight fully functional coprocessors called Synergistic Processing Elements (SPEs)
- a specialized high-bandwidth circular data bus connecting the PPE, input/output elements, and the SPEs; this bus is called the Element Interconnect Bus (EIB)
To achieve the high performance needed for mathematically intensive tasks—such as decoding/encoding MPEG streams; generating or transforming three-dimensional data; and undertaking Fourier analysis of data—the Cell processor marries the SPEs and the PPE via an EIB to give access, via fully cache-coherent DMA (direct memory access), to both main memory and external data storage. To make the best of EIB—and to overlap computation and data transfer—each of the nine processing elements (i.e., PPE and SPEs) is equipped with a DMA engine. Since the SPE's load/store instructions can access only its own local scratchpad memory, each SPE depends entirely on DMA to transfer data to and from main memory and other SPEs' local memories. A DMA operation can transfer one or more blocks: either a single block up to 16 KB in size, or a list of 2 to 2048 such blocks. A major design decision in the Cell's architecture is the use of DMA as a central means of intra-chip data transfer, with the goal of enabling maximal asynchrony and concurrency in data processing inside a chip.
The PPE, which is capable of running a conventional operating system, has control over the SPEs; it can start, stop, interrupt, and schedule processes running on these SPEs. To this end, the PPE has additional instructions related to controlling the SPEs. Unlike SPEs, the PPE can read and write main memory and the local memories of SPEs through standard load/store instructions. The SPEs are not fully autonomous: they require priming by the PPE before they can do any useful work. Most of the system's power comes from the SPEs; therefore, the use of DMA for data transfer, along with the limited local memory footprint of each SPE, poses a major challenge to software developers wishing to make the most of the system's power. This situation demands careful hand-tuning of programs to extract maximal performance from this central processing unit (CPU).
The PPE-and-bus architecture includes various modes of operation, providing different levels of memory protection, thereby allowing areas of memory to be protected from access by specific processes running on the SPEs or the PPE.
Both the PPE and the SPE use reduced instruction set computer (RISC) architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general-purpose register (GPR) set, a 64-bit floating-point register (FPR) set, and a 128-bit AltiVec register set. The SPE contains 128-bit registers only. These can be used for one of two purposes: scalar data types ranging from 8 to 64 bits in size; or single instruction, multiple data (SIMD) computations on various integer and floating-point formats. System memory addresses for both the PPE and the SPE are expressed as 64-bit values. Local store addresses internal to the SPU (Synergistic Processor Unit) processor are expressed as a 32-bit word. In documentation relating to Cell, a word is always taken to mean 32 bits, a doubleword means 64 bits, and a quadword means 128 bits.
PowerXCell 8i
In 2008, IBM announced a variant of the Cell called the PowerXCell 8i, which is available in the QS22 blade server by IBM. The PowerXCell is manufactured on a 65 nm process; in addition, it adds support for up to 32 GB of slotted Double Data Rate 2 (DDR2) memory, as well as dramatically improving double-precision floating-point performance on the SPEs—from a peak of about 12.8 billion floating point operations per second (GFLOPS) to 102.4 GFLOPS total for eight SPEs; this is the same peak performance as that of the NEC SX-9 vector processor released around the same time. The IBM Roadrunner supercomputer, the world's fastest during 2008–2009, consisted of 12,240 PowerXCell 8i processors, along with 6,562 AMD Opteron processors. The PowerXCell-8i-powered supercomputers also dominated all of the top 6 "greenest" systems in the Green500 list, with the highest MFLOPS/watt ratio supercomputers in the world. In addition to use in the QS22 and supercomputers, the PowerXCell processor is also available as an accelerator on a PCI Express card, and it is used as the core processor in the QPACE supercomputer project.
Since the PowerXCell 8i removed the Rambus memory interface, in addition to adding significantly larger DDR2 memory interfaces and enhanced SPEs, the chip layout needed to be reworked; this resulted in a larger chip die and larger packaging.
Architecture
While the Cell chip can have a number of different configurations, the basic configuration is a multi-core chip composed of one Power Processing Element (PPE) (sometimes called "Processing Element" or "PE"), and multiple Synergistic Processing Elements (SPEs). The PPE and SPEs are linked together by an internal high-speed bus named "Element Interconnect Bus" (EIB).
Power Processing Element (PPE)
The PPE is the CPU core that is PowerPC-based, dual-issue, in-order, and two-way simultaneous-multithreaded; it has a 23-stage pipeline acting as the controller for eight SPEs, which handle most of the computational workload. The PPE has limited out-of-order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems because of its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating-point code execution. The PPE contains a 32-KiB, level-1 instruction cache; a 32-KiB, level-1 data cache; and a 512-KiB, level-2 cache. The size of a cache line is 128 bytes in all caches. Additionally, IBM has included the following elements:
The PPE consists of three main units: an instruction unit (IU), an execution unit (XU), and a vector/scalar execution unit (VSU). The IU contains an L1 instruction cache, branch prediction hardware, instruction buffers, and dependency checking logic. The XU contains integer execution units (FXU) and a load-store unit (LSU). The VSU contains all of the execution resources for FPU and VMX. Each PPE can complete two double-precision operations per clock cycle using a scalar fused-multiply-add instruction, which translates to 6.4 GFLOPS at 3.2 GHz; or eight single-precision operations per clock cycle with a vector fused-multiply-add instruction, which translates to 25.6 GFLOPS at 3.2 GHz.
Xenon in Xbox 360
The PPE was designed specifically for the Cell processor, but during development, Microsoft approached IBM wanting a high-performance processor core for the Xbox 360. IBM agreed and built the tri-core Xenon processor, based on a slightly modified version of the PPE with added VMX128 extensions.