The MOS Technology 6502 is an 8-bit microprocessor that was designed by a small team led by Chuck Peddle for MOS Technology and was launched in September 1975. The design team had formerly worked at Motorola on the Motorola 6800 project; the 6502 is essentially a simplified, less expensive and faster version of that design using depletion-load NMOS technology that made using the microchip in computers much cheaper.
When it was introduced, the 6502 was the least expensive microprocessor on the market by a considerable margin. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as the 6800 or Intel 8080. Its introduction caused rapid decreases in pricing across the entire processor market. Along with the Zilog Z80, it sparked a series of projects that resulted in the home computer revolution of the early 1980s.
Home video game consoles and home computers of the 1970s through the early 1990s, such as the Atari 2600, Atari 8-bit computers, Apple II, Nintendo Entertainment System, Commodore 64, Atari Lynx, BBC Micro and others, as well as various Atari arcade video games including Asteroids, Centipede and Missile Command, use the 6502 or variations of the basic design. Soon after the 6502's introduction, MOS Technology was purchased outright by Commodore International, who continued to sell the microprocessor and licenses to other manufacturers. In the early days of the 6502, it was second-sourced by Rockwell and Synertek, and later licensed to other companies.
In 1981, the Western Design Center started development of a CMOS version, the 65C02. This continues to be widely used in embedded systems, with estimated production volumes in the hundreds of millions.
History and use
Genesis at Motorola
Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. Bennett hired Chuck Peddle in 1973 to do architectural support work on the 6800 family products already in progress. Bennett already was at work on what became the 6800. "He hired me," Peddle says of Bennett, "to do the architectural support work for the product he'd already started." … Peddle says. "Motorola tried to kill it several times. Without Bennett, the 6800 would not have happened, and a lot of the industry would not have happened, either." Peddle contributed in many areas, including the design of the 6850 asynchronous serial interface.
Peddle would accompany Motorola salespeople on customer visits, and found that customers were put off by the high cost of the microprocessor chips. At the same time, these visits invariably resulted in the engineers he presented to producing lists of required instructions that were much smaller than "all these fancy instructions" that had been included in the 6800. Peddle and other team members started outlining the design of an improved feature, reduced-size microprocessor. At that time, Motorola's new semiconductor fabrication facility in Austin, Texas, was having difficulty producing MOS chips, and mid-1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the Mesa, Arizona employees were displeased with the upcoming relocation to Austin.
Motorola's Semiconductor Products Division management showed no interest in Peddle's low-cost microprocessor proposal. Eventually, Peddle was given an official letter telling him to stop working on the system. Peddle responded to the order by informing Motorola that the letter represented an official declaration of "project abandonment", and as such, the intellectual property he had developed to that point was now his. The 6502 was designed by many of the same engineers that had designed the Motorola 6800 microprocessor family.
In a November 1975 interview, Motorola's Chairman, Bob Galvin, ultimately agreed that Peddle's concept was a good one and that the division missed an opportunity, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. The new group vice president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions."
MOS Technology
Peddle began looking outside Motorola for a source of funding for this new project. He initially approached Mostek CEO L. J. Sevin, but was declined. Sevin later admitted this was because he was afraid Motorola would sue them.
While Peddle was visiting Ford Motor Company on one of his sales trips, Bob Johnson, later head of Ford's engine automation division, mentioned that their former colleague John Paivinen had moved to General Instrument and taught himself semiconductor design. Paivinen then formed MOS Technology in Valley Forge, Pennsylvania in 1969 with two other executives from General Instrument, Mort Jaffe and Don McLaughlin. Allen-Bradley, a supplier of electronic components and industrial controls, acquired a majority interest in 1970. The company designed and fabricated custom ICs for customers and had developed a line of calculator chips.
After the Mostek efforts fell through, Peddle approached Paivinen, who "immediately got it". On 19 August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcom, Ray Hirt, Terry Holdt, and Wil Mathys left Motorola to join MOS. Mike Janes joined later. Of the seventeen chip designers and layout people on the 6800 team, eight left. The goal of the team was to design and produce a low-cost microprocessor for embedded applications and to target as wide as possible a customer base. This would be possible only if the microprocessor was low cost, and the team set the price goal for volume purchases at $5. Mensch later stated the goal was not the processor price itself, but to create a set of chips that could sell at $20 to compete with the recently introduced Intel 4040 that sold for $29 in a similar complete chipset.
Chips are produced by printing multiple copies of the chip design on the surface of a wafer, a thin disk of highly pure silicon. Smaller chips can be printed in greater numbers on the same wafer, decreasing their relative price. Additionally, wafers always include some number of tiny physical defects that are scattered across the surface. Any chip printed in that location will fail and has to be discarded. Smaller chips mean any single copy is less likely to be printed on a defect. For both of these reasons, the cost of the final product is strongly dependent on the size of the chip design.
The original 6800 chips were intended to be 180 by 180 mils (4.6 mm × 4.6 mm), but layout was completed at 212 by 212 mils (5.4 mm × 5.4 mm), or an area of 29.0 mm2. For the new design, the cost goal demanded a size goal of 153 by 168 mils (3.9 mm × 4.3 mm), or an area of 16.6 mm2, roughly half that of the 6800. Several new techniques would be needed to hit this goal.
Moving to NMOS
Two significant advances arrived in the market just as the 6502 was being designed that provided significant cost reductions. The first was the move to depletion-load NMOS. The 6800 used an early NMOS process, enhancement mode, that required three supply voltages. One of the 6800's headlining features was an onboard voltage doubler that allowed a single +5 V supply be used for +5, −5 and +12 V internally, as opposed to other chips of the era like the Intel 8080 that required three separate supply pins. While this feature reduced the complexity of the power supply and pin layout, it still required separate power lines to the various gates on the chip, driving up complexity and size. By moving to the new depletion-load design, a single +5 V supply was all that was needed, eliminating all of this complexity.
A further advantage was that depletion-load designs used less power while switching, thus running cooler and allowing higher operating speeds. Another practical offshoot is that the clock signal for earlier CPUs had to be strong enough to survive all the dissipation as it traveled through the circuits, which almost always required a separate external chip that could supply a powerful signal. With the reduced power requirements of depletion-load design, the clock could be moved onto the chip, simplifying the overall computer design. These changes greatly reduced complexity and the cost of implementing a complete system.
A wider change taking place in the industry was the introduction of projection masking. Previously, chips were patterned onto the surface of the wafer by placing a mask on the surface of the wafer and then shining a bright light on it. The masks often picked up tiny bits of dirt or photoresist as they were lifted off the chip, causing flaws in those locations on any subsequent masking. With complex designs like CPUs, 5 or 6 such masking steps would be used, and the chance that at least one of these steps would introduce a flaw was very high. In most cases, 90% of such designs were flawed, resulting in a 10% yield. The price of the working examples had to cover the production cost of the 90% that were thrown away.
In 1973, Perkin-Elmer introduced the Micralign system, which projected an image of the mask on the wafer instead of requiring direct contact. Masks no longer picked up dirt from the wafers and lasted on the order of 100,000 uses rather than 10. This eliminated step-to-step failures and the high flaw rates formerly seen on complex designs. Yields on CPUs immediately jumped from 10% to 60 or 70%. This meant the price of the CPU declined roughly the same amount and the microprocessor suddenly became a commodity device.
MOS Technology's existing fabrication lines were based on the older PMOS technology, they had not yet begun to work with NMOS when the team arrived. Paivinen promised to have an NMOS line up and running in time to begin the production of the new CPU. He delivered on the promise, the new line was ready by June 1975.
Design notes
Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. A September 1975 article in EDN magazine gives this summary of the design:
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
The main change in terms of chip size was the elimination of the tri-state drivers from the address bus outputs. A three-state bus has states for 1, 0 and high impedance. The last state is used to allow other devices to access the bus, and is typically used for multiprocessing, or more commonly in these roles, for direct memory access (DMA). While useful, this feature is expensive in terms of on-chip circuitry. The 6502 simply removed this feature, in keeping with its design as an inexpensive controller being used for specific tasks and communicating with simple devices. Peddle suggested that anyone who required this style of access could implement it with a 74158.
The next major difference was to simplify the registers. To start with, one of the two accumulators was removed. General-purpose registers like accumulators have to be accessed by many parts of the instruction decoder, and thus require significant amounts of wiring to move data to and from their storage. Two accumulators makes many coding tasks easier but costs the chip design itself significant complexity. Further savings were made by reducing the stack register from 16 to 8 bits, meaning that the stack could only be 256 bytes long, which was enough for its intended role as a microcontroller.
The 16-bit IX index register was split in two, becoming X and Y. More importantly, the style of access changed. In the 6800, IX held a 16-bit address which was offset by an 8-bit number stored with the instruction and added to the address. In the 6502 (and most other contemporary designs), the 16-bit base address was stored in the instruction, and the 8-bit X or Y was added to it.
Finally, the instruction set was simplified, simplifying the decoder and control logic. Of the original 72 instructions in the 6800, 56 were implemented. Among those removed were instructions that operated between the 6800's two accumulators, and several branch instructions inspired by the PDP-11.
The chip's high-level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the layout was a very manual process done with colored pencils and vellum paper. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the fabrication process. Given the size limits, the entire chip design had to be constantly considered. Mensch and Paivinen worked on the instruction decoder while Mensch, Peddle and Orgill worked on the ALU and registers. A further advance, developed at a party, was a way to share some of the internal wiring to allow the ALU to be reduced in size.
Despite their best efforts, the final design ended up being larger than the original target. The first 6502 chips were 168 by 183 mils (4.3 mm × 4.6 mm), for an area of 19.8 mm2. The original version of the processor had no rotate right (ROR) capability, so the instruction was omitted from the original documentation. The next iteration of the design shrank the chip and added the rotate right capability, and ROR was included in revised documentation.